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e-mail deano977 at yahoo dot com
Digital electronics design verification engineer with over six years of experience in the field of microprocessor verification.
Work Experience
·ARM Ltd., Cambridge
October 2000 - present
Staff Engineer, CPU Group - verification of the latest ARM AMBA AHB-based RISC processor cores, including ARM922T, ARM946E-S, ARM926EJ-S, ARM1156T2(F)-S, Cortex A-8, ARM11MPCore. Extensive experience of programming using ARM assembler in a Unix/Linux environment. In-depth knowledge of the ARM architecture. Debug of Verilog designs using the Cadence NC, Synopsys VCS, Mentor Modelsim simulation tools; also Novas Verdi as a front-end debugging solution. Four plus years of CPU block testbench experience with Verisity's Specman tools and the e programming language, also creation and maintenance of verilog testbench components.
Significant experience in working with sites across different timezones.
Training courses completed include:
· Verilog
· C for Embedded Applications
· Comprehensive Specman
· Comprehensive Perl
· Fundamentals of C++
· SystemC
· SystemVerilog
(training providers Doulos and Feabhas)
Major projects include:
Assignment to Bangalore - June 2006 to October 2006
Medium term assignment to work with ARM's Indian CPU Design Verification team, acting as a general consultant and line manager, with specific stakeholder role in one project in addition to normal project work on the verification of ETM11CS for MPCore, supervising an engineer in Bangalore and liaising with the rest of the project team in France and the UK.
Cortex A-8 Embedded Trace Macrocell - December 2003 to March 2006
My work on this project involved development from scratch of a unit level test environment for the Cortex A-8 Embedded Trace Macrocell in e, including directed random stimulus and cycle accurate checkers. I defined and implemented (using SystemVerilog) functional coverage for the unit, supervising three other engineers who also worked on coverage implementation. I also defined the strategy for top-level testing of the ETM with the core, and worked with the rest of the Cortex A-8 team, who were based in Texas, to implement this strategy, including adding testbench components, and adding a new random testing strategy. I also remotely supervised a junior engineer working on ETM verification for the second half of the project.
ARM1156 Core - April to November 2003
This processor was the first implementation of the Thumb2 instruction set. My work involved extending an existing Specman-based testbench for the integer core to include the new instruction set extensions, including random stimulus generation, functional modelling of the instructions and checking of their operation, and functional coverage over the ISA.
ARM926EJ-S
I was involved in writing the device-specific assembler tests for the ARM926EJ-S core, and supported the product's verification deliverables, used successfully by over 20 partners, for a year after the core's release.
·Jennic Ltd., Sheffield
Ten week project over summer 2000, using Verilog to implement a Reed-Solomon
Forward Error Correction system to run at STM-16 speed. Simulations run using the Modelsim
and Active-HDL packages. System synthesised using Leonardo Spectrum.
Project work used as initial investigation work for 40Gb/s FEC system (see Jennic press release for details).
Education
· Sheffield
University September 1999 - September 2000
One-year Msc (Eng) in Data Communications.
Modules include: Foundations of Object-Oriented Programming (Java), Computer
Networks, Analysis of Networks, Communication Principles, Digital Communications,
RF & Optical Communications, Mobile Networks & Low-Level Protocols,
Broadband Communications & Internetworking.
Distinction level obtained on taught part of course - 13.7/16, i.e. 69%.
Final project mark 13/16, i.e. 67-69%.
Project work:
Maxi project – telephone treatment randomisation service for Northern
General Hospital, Sheffield
Systems Architecture Design - implementation of a V.22 modem on a DSP
board
Summer project – design of a Forward Error Correction system using Verilog for implementation
in an FPGA at Jennic, Ltd.
· Cambridge
University September 1996 – June 1999
BA (Hon) in Natural Sciences (Astrophysics)
1st year subjects – Physics, Chemistry, Geology, Maths –
overall grade 2.1
2nd year subjects – Advanced Physics, Maths – overall grade
2.2
3rd year specialisation – Astrophysics – grade 2.2
· Malbank 6th form College,
Nantwich September 1994 – June 1996
6 A levels with Pure Maths, Pure & Applied Maths, Further Pure
& Applied Maths, Physics and General Studies at A grade and Chemistry
at B grade.
Awarded John Lodge Prize for outstanding achievment at advanced level.
· Brine Leas High School, Nantwich
September 1989 – June 1994
10 GCSE’s, 7 at A* level including Nuffield Combined Sciences, French,
German, History, English Language and Information Technology plus A/O Maths
at A grade.
Interests
Music - ex-secretary of a Cambridge
University Society, involved in planning, publicising and executing
regular, successful club nights and other social activities
Sports - playing and watching football, part of badminton team for
high school, 6th form, and university
Personal
Date of Birth: 27/9/77 Married Full UK Driving License